This invention relates generally to a method and apparatus for testing integrated circuits. More specifically, this invention relates to a method and apparatus for testing for latch-up in integrated circuits.
A major problem in integrated circuits is a phenomenon known as latch-up. Latch-up occurs when triggering current causes complementary bipolar structures in the integrated circuit to interact electrically, establishing a low-resistance path, thus allowing large current to flow through the circuit. This can cause the circuit to cease functioning or even to self-destruct due to heat damage caused by high power dissipation.
Latch-up may be caused by, e.g., termainal over voltage stress, transient displacement current, ionizing radiation, impace ionization by hot electrons, or light.
A detailed explanation of latch-up is given in, e.g., Silicon Processing for the VLSI ERA, Vol. II, Chapter 6.4, Stanley Wolf, Ph.D., Lattice Press, 1990.
Various techniques have been developed for detecting latch-up in integrated circuits.
One known technique for detecting latch-up is Optical Beam Induced Current (OBIC) methodology. A device for performing this technique is shown in FIG. 1A. The device includes, among other features, a scanning unit (SU) 110, an amplifier 130, and a signal processing unit (SPU) 140. A rastorized optical beam, e.g., a laser produced by the SU 110 is scanned across a specimen, such as an integrated circuit (IC) 120. A laser scanning microscope (LSM) may be used as the SU 110 to produce the laser. When the optical beam impacts the IC surface, electron-hole pairs are generated, in effect inducing a current. Information regarding the position of the optical beam is fed to the SPU 140. While the laser scans, the Vcc or Vss current induced by the optical beam is amplified by the amplifier 130 and recorded and synchronized with the position of the optical beam in the SPU 140. Information regarding the measured current and the positioning of the optical beam is converted into an image by the SPU 140, with the highest current being represented as the highest intensity. Low current effectively becomes transparent. The representative image of current is overlaid with an optical image generated by the LSM. The resulting image indicates where high current exists in the IC, which indicates where latch-up has occurred in the IC.
FIG. 1B depicts a graph indicating where latch-up occurs using the OBIC method. In FIG. 1B, the x-axis represents a position in one direction, e.g., a horizontal direction, on the surface of the IC, and the y-axis represents the current. As can be seen from FIG. 1B, a high current exists at a position x1, indicating latch-up. Several of these graphs may be produced along several such lines, across the surface of the IC. The results may be combined to produce a two dimensional image, indicating where latch-up occurs in the IC.
An example of OBIC technology is given in U.S. Pat. No. 4,812,748. As described in this patent, the LSM is fixed on a point, and the test program is run. The current is monitored, and if the current does not exceed a threshold current setting, the LSM moves to a new focal spot and starts over. If the threshold current is exceeded, the method is repeated using a reduced intensity laser over the localized region.
OBIC technology is also described in U.S. Pat. Nos. 4,902,966, 5,334,540 5,430,305, and 5,493,236.
Another technique for detecting latch-up is a modulated laser. A device for performing this technique is shown in FIG. 2A. According to this method, a laser beam is scanned across the surface of an IC, the IC is powered by a power supply (PS) 160, and an SPU 145 varies the power of the modulated laser 105 to maintain a constant current. The power is lowered if the current rises. The SPU 145 processes this information to produce an image. When the current drops, this indicates latch-up.
FIG. 2B depicts a graph indicating where latch-up occurs using a modulated laser. In FIG. 2B, the x-axis represents a position on the IC, and the y-axis represents power. As can be seen from FIG. 2B, at a position x2 on the IC, the power drops, indicating latch-up. In a manner similar to that explained above with regard to FIG. 1B, several of these graphs can be produced along lines across the IC, and the results can be combined to produce a two-dimensional image, indicating where latch-up occurs in the IC.
Conventional methods of latch-up testing and analysis of integrated circuits are time consuming, taking days or even weeks to set up and complete, due to the sensitivity of the equipment used. Also, standard testing methods are not capable of testing most internal nodes or under many different operational conditions, because of the preciseness required to obtain results.
There is thus a need for a technique for testing integrated circuits that may be performed quickly and under many different operational conditions.
It is therefore an object of the present invention to provide a technique for quickly detecting latch-up in an integrated circuit. It is yet another object of the present invention to provide a technique capable of detecting latch-up in an integrated circuit under many different operational conditions.
According to an exemplary embodiment, this and other objects are met by a method and apparatus for detecting latch-up in a circuit, e.g., an integrated circuit. According to exemplary embodiments, an optical beam is scanned across the surface of the integrated circuit, power is supplied to the integrated circuit, and the power of the power supply is monitored. When the power reaches a predetermined threshold, an image of the integrated circuit is captured. The captured image is compared with an image taken with the laser off to determine where latch-up occurs on the integrated circuit.